Delay lines are typically incorporated into electronic devices to accommodate inherent differences in electronic components due to fabrication imperfections. A conventional delay line typically utilizes the input to output delay of one or more inverters arranged in series to accommodate the inherent differences of electronic components. The number and type of inverters used is determined by the required delay time. However, the overall delay time resulting from the one or more serial inverters is subject to process and/or environmental variations such as process corners (i.e., process variations arising during fabrication), changes in temperature during operation and power supply fluctuations. When variations in the process and environmental factors are aggregated together, the resulting delay time may vary from the expected delay time by as much as fifty percent. Faced with such inconsistencies, circuit and device designers are forced to over-design their circuits or devices, with respect to the original specifications, to accommodate the resulting overall delays experienced.
For example, in a high-speed pipe line analog-to-digital converter (ADC) with a clock frequency of 25 Megahertz (MHz), the duration of a clock pulse is 20 nanoseconds (nS). Of this 20 nS, 4 nS is typically allocated to the non-overlapping time of the non-overlapping clock (thereby allowing time for the comparator to settle), 2 nS is typically allocated to a slew-rate limiting period of the operational amplifier (opamp) settling time, 1 nS is typically allocated to the bottom-plate sampling edge, leaving only 12 nS for a bandwidth limiting period of the opamp settling time. If a conventional delay line is used to control the 4 nS non-overlapping time of the non-overlapping clock, the actual delay time can vary between approximately 2.5 nS to 6 nS. In this case the designer would be forced to over design the comparator to ensure that the comparator is capable of settling within 2.5 nS in the worst case, and would have to over design the opamp to ensure that the opamp can settle within 10 nS (rather than the 12 nS) in light of the uncertainty of the non-overlapping time.
As a second example, FIG. 1 depicts a pixel-array readout scheme 100 that is well understood by one of ordinary skill in the art. For example, and without limitation, the pixel-array readout scheme of FIG. 1 includes one hundred columns 105. The pixel array is read out row-by-row. Each time a row is read, the voltage values from the pixel array are stored in capacitors 110 located in sampling columns. In order to read the voltage values stored in the sampling columns, the sampling columns (cs) are connected to the readout circuitry column by column through column select switches 115. The column select switches 115 are controlled by the column address. The charges stored in the capacitors 110 are then “crow-bared” out to the readout circuitry through crow-bar (cb) switches 120.
FIG. 2 illustrates a desired timing relationship between the sampling columns (cs) and the crow-bar (cb) switches. The time t1 is typically used to reset the first stage of the readout circuitry. The time t2 is reserves as a time margin to ensure the current crow-bar is completed prior to any column address change. Typically, cs1-cs100 and cb1-cb100 are derived from a column address and a crow-bar clock. In this case, the falling edge of cb is typically, for example, several nanoseconds ahead of the falling edge of cs. The falling edge of cs is controlled by a delay line in a clock generation block. In light of power supply voltage variations, process variations and environmental temperature variations, a design margin must be include to ensure cb falls before the column address changes. However, including this design margin reduces the available time for t1 resulting in a reduced reset time for the first stage of the readout circuitry. This reduced reset time may manifest itself in column-wise fixed pattern noise.
A need exists to reduce or eliminate uncertainties in delay times caused by process and environmental variations. A further need exists to accurately predict the resulting delay times for circuits or devices added to overcome inherent differences due to device fabrication.